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ISLA214S50
15
FN7973.2
April 25, 2013
Theory of Operation
Functional Description
The device is based upon a 14-bit, 250MSPS ADC converter core
that utilizes a pipelined successive approximation architecture
(see Figure 28). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied.
Power-On Calibration
The ADC core(s) perform a self-calibration at start-up. An internal
power-on-reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and digital supply
voltages are above a threshold. The following conditions must be
adhered to for the power-on calibration to execute successfully:
A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
DNC pins must not be connected
SDO has an internal pull-up and should not be driven externally
RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
SPI communications must not be attempted during
calibration, with the only exception of performing read
operations on the cal_done register at address 0xB6.
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 29. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. During calibration the JESD204 transmitter PLL is not
locked to the ADC sample clock, so the CML outputs will toggle at
an undetermined rate. Normal operation is resumed once
calibration is complete.
At 250MSPS the nominal calibration time is 280ms, while the
maximum calibration time is 550ms.
FIGURE 28. ADC CORE BLOCK DIAGRAM
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5- BIT
FLASH
6- STAGE
1.5- BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3- BIT
FLASH
+
–
FLASH
2.5-BIT
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